Description

ESD TR5.4-02 – Determination of CMOS Latch-up Susceptibility, Transient Induced Latch-Up – Technical Report No. 2

This technical report is intended to provide background information pertaining to the development of the transient latch-up standard practice.

Product Details

Published:

2008

Number of Pages:

62

File Size:

1 file , 1.3 MB

Note:

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